Technique to control tunneling currents in dram capacitors, cells, and devices

ABSTRACT

Structure and methods for the use of PMOS devices, with p-type polysilicon gates or metal gates with large electron affinities or work functions are provided. These PMOS devices minimize tunneling leakage currents in DRAM capacitors, cells and devices, as well as conserve power supply currents to minimize power dissipation. A memory cell is provided which utilizes p-type semiconductor or metal gates or capacitor plates with work functions larger than those of n-type doped polysilicon (4.1 eV) or the commonly used aluminum metal in MOS technology (4.1 eV). The memory cell includes a PMOS transistor. The PMOS transistor includes a first source/drain region and a second source/drain region separated by a channel region. The first and the second source/drain region include source/drain regions having a large work function. The PMOS transistor has a gate opposing the channel region and separated therefrom by a gate insulator. The gate includes a gate having a large work function. The memory cell further includes a storage device, or capacitor, coupled to the second source/drain region. The capacitor includes a first storage node and a second storage node. At least one of the first and the second storage nodes includes a storage node having a large work function.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is related to the following co-pending, commonly assigned U.S. patent applications: L. Forbes, “P-CHANNEL DYNAMIC FLASH MEMORY CELLS WITH ULTRATHIN TUNNEL OXIDES,” Micron 99-0946, Ser. No. ______; L. Forbes, “STATIC NVRAM MEMORY CELL WITH ULTRATHIN TUNNEL OXIDES,” Micron 99-0945, Ser. No. ______; L. Forbes and K. Y. Ahn, “LOW VOLTAGE FIELD (IN SYSTEM) PROGRAMMABLE LOGIC ARRAY WITH ULTRATHIN TUNNEL OXIDES,” Micron 99-1064, Ser. No. ______; L. Forbes and k. Y. Ahn, “LOW VOLTAGE PROGRAMMABLE MEMORY ADDRESS AND DECODE CIRCUITS WITH ULTRATHIN TUNNEL OXIDES FOR FAULT CORRECTION,” Micron 99-1076, Ser. No. ______, each of which disclosure is herein incorporated by reference.

FIELD OF THE INVENTION

[0002] The present invention relates generally to integrated circuits, and in particular to techniques to control tunneling currents in DRAM capacitors, cells, and devices.

BACKGROUND OF THE INVENTION

[0003] Field-effect transistors (FETs) are typically produced using a standard complementary metal-oxide-semiconductor (CMOS) integrated circuit fabrication process. As is well known in the art, such a process allows a high degree of integration such that a high circuit density can be obtained with the use of relatively few well-established masking and processing steps. A standard CMOS process is typically used to fabricate FETs that each have a gate electrode that is composed of -type conductively doped polycrystalline silicon (polysilicon) material or other conductive materials.

[0004] The modern memory cell is composed of one transistor, such as the above described FET, and one capacitor. This modern form of the memory cell is referred to as dynamic random access memory (DRAM). In a DRAM, stored charge on the capacitor represents represent a binary one or zero while the transistor, or FET, acts as the switch interposed between the bit line or digit line and capacitor. The capacitor array plate or common node is typically charged to Vcc/2 (Vcc also written as Vdd), and therefore the charge stored on the capacitor for logic 1 is q=C *Vcc/2 and for a logic zero the stored charge is q=−C*Vcc/2 the charge is negative with respect to Vcc/2 common node voltage. The bit line or digit line connects to a multitude of transistors. The gate of the access transistor is connected to a word or row line. The wordline connects to a multitude of transistors.

[0005] In conventional DRAMS using NMOS access transistors, the transmission of a 1 or Vcc in writing a 1 into the capacitor (i.e., charging the capacitor to Vcc, though the total voltage across the capacitor is Vcc/2 as the array plate is kept at Vcc/2) is degraded unless a gate voltage higher than Vcc or Vdd is used. If the gate voltage was just kept at Vdd or Vcc the amount of voltage on the capacitor plate connected to the transistor would only be Vdd−Vtn (where Vtn is the threshold voltage). Using an n-channel access devices requires the gate voltage of the n-channel transistor be raised to Vdd+Vtn where Vtn is the threshold voltage of the NMOS transistor. This will allow the capacitor plate to see a full Vdd, e.g. [(Vdd+Vtn)−Vtn]=Vdd. Similarly for the PMOS access transistors the transmission of a zero or Vss is degraded, and the voltage of the PMOS gate has to be lowered to Vss−Vtp. The preferred voltage applied to the gate of the PMOS device when turned on in this invention is −Vtp, or more negative than Vtp. Applying this voltage to the PMOS transistor turns it on and therefore a 1 or a 0 can be written into the capacitor. If the plate connected to the PMOS is charged to Vcc or Vdd then the capacitor stores a 1, and if the plate connected to the PMOS is charged Vss then the capacitor stores a 0. Normally the array plate of the capacitor is tied to Vcc/2 and the voltage across the capacitor is Vcc/2.

[0006] The use of PMOS devices in DRAM memory cells is in itself not new, in fact the original patent (U.S. Pat. No. 3,387,286 “FIELD EFFECT TRANSISTOR MEMORY,” R. H. Dennard, Jun. 4, 1968) described both the use of NMOS and PMOS devices. In 1970, the newly formed Intel Company publicly released the 1103, the first DRAM (Dynamic Random Access Memory) chip (1K bit PMOS dynamic RAM ICs), and by 1972 it was the best selling semiconductor memory chip in the world, defeating magnetic core type memory. The first commercially available computer using the 1103 was the HP 9800 series. These devices however were based on an old technology with gate oxides in the range of 1000 angstroms, 0.1 micron, or 100 nm. PMOS devices were used because of the normally accumulated surface on n-type wafers, techniques had not yet been fully developed to control the surface inversion in the field regions of p-type wafers. With such thick gate insulators and capacitor dielectrics there was and is little consideration and concern about tunneling leakage currents.

[0007] With the development of the LOCOS process and field implantations to control surface inversion on p-type wafers the industry changed to NMOS technology and then CMOS technology on p-type wafers. Subsequent developments and scaling of devices to below 0.1 micron, or 100 nm, dimensions have resulted in the use of ultrathin gate oxides and capacitor dielectric insulators, as low as 12 angstroms, or 1.2 nm. Such ultrathin insulators can result in large tunneling currents, in the case of silicon oxide as large as 1.0A/cm² (S. M. Sze, “Physics of semiconductor devices,” Wiley, N.Y., 1981, pp. 402-407; T. P. Ma et al., “Tunneling leakage current in ultrathin (<4 nm) nitride/oxide stack dielectrics,” IEEE Electron Device Letters, vol. 19, no. 10, pp. 388-390, 1998). While such leakage or tunneling currents may not cause faults in microprocessors and logic circuits (R. Chau et al., “30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays,” IEEE Int. Electron, Devices Meeting, San Francisco, pp. 45-48, December 2000) they are intolerable in DRAM devices, capacitors and cells.

[0008]FIG. 1A, illustrates a conventional DRAM cell 100. As shown in FIG. 1A, the conventional DRAM cell includes a transistor 101 and a capacitor cell 102. A gate 103 for the transistor 101 is separated from the channel 104 of the transistor 100 by an insulator 106, such as an oxide. The channel region 104 of the transistor separates a source region, or first source/drain region 108 from a drain region, or second source/drain region 110. As shown in FIG. 1A, the drain region 110 is coupled to a first plate or capacitor plate 112 of the capacitor cell 102. A second plate, or array plate 114 of the capacitor cell 102 is coupled to Vdd/2. As stated above, these cells depend upon charge storage on capacitance nodes. FIG. 1A illustrates tunneling currents which are leakage currents that will discharge the cells resulting in shortened retention times and/or lost data and faults. FIG. 1A further illustrates that a cause of leakage currents is tunneling from the source/drain of the transfer device which is connected to the capacitor plate to the gate of the transistor when the transistor is off.

[0009] As illustrated in FIG. 1B, if a zero is stored in the capacitor cell 102, then the drain 110 of the transistor will be at zero or ground potential, but the gate 103 of the transistor when turned off will be a potential Vdd. This results in a large positive potential between the source/drain at ground, e.g. drain 110 and the gate 103 at potential+Vdd which can result in tunneling leakage currents. These leakage currents would tend to make the capacitor electrode more positive and can result in data errors.

[0010] Also, tunneling leakage currents from the gate 103 to substrate/channel 104 when the transistor 101 is turned on with a large negative gate 103 to source 108 voltage will result in excessive gate currents. While the tunneling current of one gate 103 may be very small, modern DRAM arrays have a large number of capacitor cells 102 and transfer devices 101. Summed over an entire array, this leakage current, which may be up to 1A/cm², will result in excessive power supply currents and power dissipation.

[0011] Therefore, there is a need in the art to provide improved techniques for controlling tunneling currents in DRAM capacitors, cells and devices. Such improved techniques should take into power supply currents and power dissipation issues.

SUMMARY OF THE INVENTION

[0012] The above mentioned problems with tunneling leakage currents in DRAM capacitors, cells and devices, as well as the power supply current and power dissipation issues are addressed by the present invention and will be understood by reading and studying the following specification. This disclosure describes the use of PMOS devices, with p-type polysilicon gates or metal gates with large electron affinities or work functions as transfer devices in DRAM cells and the use of p-type polysilicon plates or metal plates with large electron affinities or work functions in DRAM capacitor storage cells. The much larger tunneling barriers in these devices (at least 1.2 eV larger) than in the conventional NMOS devices and capacitor plates doped n-type will result in tunneling currents which are orders of magnitude smaller at the same electric fields across the gate and/or capacitor insulators. In fact the larger barriers and lower operating voltages will preclude Fowler-Nordhiem (F-N) tunneling and the primary tunneling mechanism will be limited to direct band to band tunneling.

[0013] In one embodiment of the present invention a novel memory cell is provided. The novel memory cell includes a PMOS transistor. The PMOS transistor includes a first source/drain region and a second source/drain region separated by a channel region. The first and the second source/drain region include source/drain regions having a large work function. The PMOS transistor has a gate opposing the channel region and separated therefrom by a gate insulator. The gate includes a gate having a large work function. The memory cell further includes a storage device, or capacitor, coupled to the second source/drain region. The capacitor includes a first storage node and a second storage node. At least one of the first and the second storage nodes includes a storage node having a large work function.

[0014] These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIGS. 1A-1B, illustrate a conventional DRAM cell.

[0016]FIG. 2 is an energy band diagram illustrating the “mid-gap” metals used for optimizing NMOS and PMOS transistor threshold voltages according to the prior art.

[0017]FIG. 3A is an energy band diagram illustrating direct band to band tunneling with low voltages across the gate oxides or gate insulators in conjunction with a p-type semiconductor gate or p-type capacitor storage nodes having large electron affinities or work functions according to the teachings of the present invention.

[0018]FIG. 3B is an energy band diagram illustrating direct band to band tunneling with low voltages across the gate oxides or gate insulators in conjunction with metal gate or metal capacitor storage nodes having large work functions according to another embodiment of the present invention.

[0019]FIG. 4 is a graph plotting electron affinity versus band gap energy of silicon, carbide, and oxygen related compounds.

[0020]FIG. 5, is a graph plotting work function versus atomic number for large work function materials.

[0021]FIG. 6 illustrates one embodiment for DRAM device, or transistor according to the teachings of the present invention.

[0022]FIG. 7 illustrates a memory cell according to the teachings of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. The embodiments are intended to describe aspects of the invention in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and changes may be made without departing from the scope of the present invention. In the following description, the terms wafer and substrate are interchangeably used to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. Both terms include doped and undoped semiconductors, epitaxial layers of a semiconductor on a supporting semiconductor or insulating material, combinations of such layers, as well as other such structures that are known in the art. The following detailed description is not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.

[0024] In the past we have disclosed the use of this direct band to band tunneling current in PMOS devices for flash memory type devices and cells (L. Forbes, “P-CHANNEL DYNAMIC FLASH MEMORY CELLS WITH ULTRATHIN TUNNEL OXIDES,” Micron 99-0946; L. Forbes, “STATIC NVRAM MEMORY CELL WITH ULTRATHIN TUNNEL OXIDES,” Micron 99-0945; L. Forbes and K. Y. Ahn, “LOW VOLTAGE FIELD (IN SYSTEM) PROGRAMMABLE LOGIC ARRAY WITH ULTRATHIN TUNNEL OXIDES,” Micron 99-1064; L. Forbes and k. Y. Ahn, “LOW VOLTAGE PROGRAMMABLE MEMORY ADDRESS AND DECODE CIRCUITS WITH ULTRATHIN TUNNEL OXIDES FOR FAULT CORRECTION,” Micron 99-1076), the intent there being to increase the endurance of flash memory type cells since direct band to band tunneling will not result in electron collisions in the oxide and damage to the oxide as occurs in F-N tunneling.

[0025] Prior art in the use of metals with work functions larger than aluminum or n-type polysilicon have been directed at so called “mid-gap” work functions which make the threshold voltages for both NMOS and PMOS devices symmetrical (see generally, B. Maiti and P. J. Tobin, “Metal gates for advanced CMOS technology,” Proc. Microelectronics Device Technology III, Santa Clara, Calif., Sep. 22-23, 1999, Soc. of Photo-Optical Instrumentation Engineers, Bellingham Wash., pp. 46-57) or the same magnitude or numeric value. This is illustrated in FIG. 2 showing the position of the Fermi level in the metal falling in the center of the silicon bandgap with no potential difference across the gate insulator. Common mid-gap metal work functions are provided by the refractory metals tungsten, W, and molydenum, Mo.

[0026]FIG. 2 is an energy band diagram illustrating the “mid-gap” metals used for optimizing NMOS and PMOS transistor threshold voltages according to the prior art. FIG. 2 is used to illustrate a metal gate 209, such as Tungsten W (work function 4.6 eV) or Molybdenum Mo (work function 4.7 eV) in a DRAM cell separated by an oxide 201 from a channel region 207 in either an n-type (PMOS transistor) or a p-type (NMOS transistor) substrate. As shown in FIG. 2, the metal/semiconductor work function differences can be expressed as follows. For NMOS devices 4.7V−5.0 eV=−0.3 eV, for PMOS devices 4.7−4.4 eV=+0.3 eV. FIG. 2 illustrates the position of the Fermi level in the metal falling in the center of the silicon bandgap with no potential difference across the gate insulator. As stated above, common mid-gap metal work functions are provided by the refractory metals tungsten, W, and molybdenum, MO. However, these prior art techniques still do not solve the problem of low leakage current, which may be up to 1A/cm², and will result in excessive power supply currents and power dissipation.

[0027] In the present invention, the intent is to utilize the larger tunneling barriers and lower voltages than used in flash memory devices to limit these tunneling leakage currents to levels which are acceptable in DRAM devices, cells and capacitors.

[0028]FIG. 3A is an energy band diagram illustrating direct band to band tunneling with low voltages across the gate oxides or gate insulators in conjunction with a p-type semiconductor gate or p-type capacitor storage nodes 309 having large electron affinities or work functions according to the teachings of the present invention. FIG. 3A illustrates a p-type semiconductor gate or capacitor storage node/plate 309 separated by an insulator, e.g. an oxide 301, from a channel region/substrate 307 or second capacitor storage node/plate 307. According to the teachings of the present invention, the p-type semiconductor gate or capacitor 309 includes polycrystalline semiconductor plates selected from the group consisting of p-doped silicon, p-doped germanium, p-doped silicon germanium compounds, p-doped silicon carbide, p-doped silicon oxycarbide compounds, p-doped gallium nitride compounds, and p-doped gallium aluminum nitride compounds. According to the teachings of the present invention, the tunneling barriers in the structure of FIG. 3A are much larger than in conventional NMOS devices and capacitor plates doped n-type. As one of ordinary skill in the art will understand upon reading this disclosure, these much larger tunneling barriers will result in tunneling currents which are orders of magnitude smaller at the same electric fields across the gate and/or capacitor insulators 301.

[0029] In fact, according to the teachings of the present invention, the larger barriers and lower operating voltages will preclude Fowler-Nordheim (F-N) tunneling and the primary tunneling mechanism will be limited to direct band-to-band tunneling.

[0030] As discussed above, a number of previous works by the current inventors have disclosed the use of direct band-to-band tunneling current in PMOS devices for flash memory type devices and cells. However, there the intent was to increase the endurance of flash memory type cells since direct band-to-band tunneling will not result in electron collisions in the oxide and damage to the oxide as occurs in F-N tunneling. FIG. 3A illustrates the direct band-to-band tunneling with low voltages across the gate oxides or gate insulators 301.

[0031] In the present invention, the intent is to use the larger tunneling barriers and lower voltages than used in flash memory devices to limit these tunneling leakage currents to levels which are acceptable in DRAM devices, cells and capacitors.

[0032]FIG. 3B is an energy band diagram illustrating direct band to band tunneling with low voltages across the gate oxides or gate insulators in conjunction with metal gate or metal capacitor storage nodes having large work functions according to another embodiment of the present invention. FIG. 3B illustrates a metal gate or metal capacitor storage node/plate 309 separated by an insulator, e.g. an oxide 301, from a channel region/substrate 307 or second capacitor storage node/plate. According to the teachings of the present invention, the metal gate or metal capacitor storage node/plate 309 includes a metal gate selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold. Alternatively, in one embodiment of the present invention, the metal gate or metal capacitor storage node/plate 309 includes a metallic nitride gate selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride.

[0033] In contrast to the previous work, the present invention utilizes p-type semiconductor or metal gates or capacitor plates with work functions larger than those of n-type doped polysilicon (4.1 eV) or the commonly used aluminum metal in MOS technology (4.1 eV). Voltages applied to the gates or plates are lower than 3.2 Volts so the primary tunneling mechanism is restricted to direct band to band tunneling (see generally, T. P. Ma et al., “Tunneling leakage current in ultrathin (<4 nm) nitride/oxide stack dielectrics,” IEEE Electron Device Letters, vol. 19, no. 10, pp. 388-390, 1998).

[0034]FIG. 4 is a graph plotting electron affinity versus band gap energy of silicon, carbide, and oxygen related compounds. As shown in FIG. 4, silicon dioxide is an insulator with a relative dielectric constant of 3.9, energy gap of approximately 9.0 eV, and electron affinity of 0.9 eV. In a conventional flash memory, electrons stored on the polysilicon floating gate see a large tunneling barrier of about 3.2 eV. This value is the difference between the electron affinities of silicon (4.1 eV) and SiO₂ (0.9 eV). This is a relative large barrier which requires high applied electric fields for electron injection. SiO has a dielectric constant close to that of SiO₂ which, as stated above, has a value near 3.9. Also, as shown in FIG. 4, SiO has a band gap of approximately 3.2 eV and an estimated electron affinity of 3.5 eV. Accordingly, as shown in FIG. 4, the x in SiOx can be varied to produce a range of electron affinities and poly-Si/a-SiOx tunneling barriers from 0.6 eV to 3.2 eV. Finally, Crystalline SiC has a band gap of ˜3 eV and an electron affinity of 3.7 eV. Amorphous SiC or a-SiC and hydrogenated, amorphous a-SiC_(x):H films have relatively low conductivity under modest applied electric fields (see generally, F. Dimichelis et al., “Doped amorphous and microcrystalline silicon carbide as wide bandgap material,” Symp. On Wide Band Gap Semiconductors, Mat. Res. Soc., Pittsburgh, Pa., pp. 675-680, 1992). Amorphous-Si_(x)C_(y)O_(z), or a-Si_(x)C_(y)O_(z), is a wide band gap insulator with a low dielectric constant (<4), comparable to SiO₂ (see generally, T. Furusawa et al., “Simple reliable Cu/low-k interconnect integration using mechanically-strong low-k dielectric material: silicon-oxycarbide,” Proc. IEEE int. Interconnect Technology Conf., pp. 222-224, June 2000). No measurements have been reported on the electron affinities of amorphous films of silicon oxycarbide but projections can be made based on the electron affinities and band gaps of SiO₂ and SiC. As shown in FIG. 4, the electron affinity of a-Si_(x)C_(y)O_(z) should vary from that of silicon dioxide (0.9 eV) to that of the silicon carbide (3.7 eV). This means that the electron barrier between the oxycarbide and silicon (sic, the difference in electron affinities of the pure silicon dioxide and pure silicon carbide) can be varied from roughly 0.4 to 3.2 eV.

[0035]FIG. 5, is a graph plotting work function versus atomic number for large work function materials. FIG. 5 is provided to note the relationship of work functions to atomic number and position in the periodic table. FIG. 5 illustrates plots the work function versus atomic number of p-type silicon, aluminum (Al), p-type germanium, cobalt (Co), nickel (Ni), rubinium (Ru), rhodium (Rh), palladium (Pd), iridium (Ir), platinum (Pt) and gold (Au).

[0036] According to the teachings of the present invention, the p-doped silicon and silicon germanium, p-doped large band-gap semiconductors, metals with large work functions, and metallic nitrides with large work functions are fabricated using conventional process techniques.

[0037]FIG. 6 illustrates one embodiment for DRAM device 600 including a transistor 601 according to the teachings of the present invention. As shown in FIG. 6, a transistor 601 is provided having a first source/drain region 608 and a second source/drain region 610. According to the embodiment shown in FIG. 6, the first 608 and the second 610 source/drain region include source/drain regions, 608 and 610, formed of a material having a large work function. A channel 607 is located between the first and the second source/drain regions, 608 and 610. A gate 609 opposes the channel 607. According to the teachings of the present invention, the gate 609 includes a gate 609 formed of a material having a large work function. A gate insulator 613 separates the gate from the channel.

[0038] Several embodiments of the present invention can be described in connection with the transistor 601 in FIG. 6. These several embodiments include a gate 609 having a large work function where the gate material is formed from the group consisting of p-type doped polycrystalline semiconductor material, large work function metals, and large work function metallic nitrides.

[0039] As stated above, one of the several embodiments of the present invention, includes the gate 609 of the transistor 601, formed of a material having a large work function, being a p-type doped polycrystalline semiconductor gate. The embodiment of the present invention, having a large work function, p-type doped polycrystalline semiconductor gate 609 can further include several subsets to this embodiment. In one subset embodiment, the large work function, p-type doped polycrystalline semiconductor gate 609 includes p-doped germanium. In another subset embodiment, the large work function, p-type doped polycrystalline semiconductor gate 609 includes p-doped silicon germanium compounds. In another subset embodiment, the large work function, p-type doped polycrystalline semiconductor gate 609 includes p-doped silicon carbide.

[0040]FIG. 6 can similarly illustrates another embodiment for DRAM device 600, or transistor 601 according to the teachings of the present invention. As shown in FIG. 6 a transistor 601 is provided having a first source/drain region 608 and a second source/drain region 610. According to the embodiment shown in FIG. 6, the first 608 and the second 610 source/drain region include source/drain regions, 608 and 610, formed of a material having a large work function. A channel 607 is located between the first and the second source/drain regions, 608 and 610. A gate 609 opposes the channel 607. According to the teachings of the present invention, the gate 609 includes a gate 609 formed of a material having a large work function. In this alternative embodiment, the gate includes a metal gate selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold. Further, the metal gate can include a metallic nitride gate selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride.

[0041] As shown in FIG. 6, the above described transistor 601 forms part of a memory cell 600. According to the teachings of the present invention, the memory cell is a DRAM cell. In one embodiment of the present invention, the gate insulator is less than 20 Angstroms thick.

[0042] As shown in FIG. 6, the memory cell 600 includes a capacitor 602 coupled to the second source/drain region 610 wherein a first 612 and a second plate 614 of the capacitor include first and second plates, 612 and 614 respectively, having a large work function. In one embodiment according to the teachings of the present invention, at least one of the first and the second plates, 612 and 614 include p-type polysilicon polycrystalline semiconductor plates. In this embodiment, the polycrystalline semiconductor plates, 612 and 614, are selected from the group consisting of p-doped silicon, p-doped germanium, p-doped silicon germanium compounds, p-doped silicon carbide, p-doped silicon oxycarbide compounds, p-doped gallium nitride compounds, and p-doped gallium aluminum nitride compounds.

[0043] In an alternative embodiment, at least one of the first and the second plates, 612 and 614 respectively include metal plates. In this embodiment, the metal plates include metal plates selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold. In still another embodiment of the present invention, the first and the second plates, 612 and 614 include metallic nitride plates. In this embodiment, the metallic nitride plates, 612 and 614 include metallic nitride plates selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride.

[0044]FIG. 7 illustrates a memory cell 700 according to the teachings of the present invention. As shown in FIG. 7, memory cell 700 includes a PMOS transistor 701 formed in an n-type well 731. As shown in FIG. 7, the PMOS transistor 701 includes a first source/drain region 708, and a second source/drain region 710, where the first and the second source/drain region, 708 and 710 include source/drain regions having a large work function. A channel is 707 located between the first and the second source/drain regions, 708 and 710. A gate 709 opposes the channel 707. The gate includes a gate having a large work function. A gate insulator 706 separates the gate from the channel 707. In one embodiment, the gate insulator 706 is less than 20 Angstroms thick. As shown in FIG. 7, the memory cell 700 further includes a capacitor 703 coupled to the second source/drain region 710 wherein a first and a second plate of the capacitor, 712 and 714 includes first and second plates having a large work function.

[0045] As described above, embodiments of the present invention include first and the second p-type polysilicon polycrystalline semiconductor plates selected from the group consisting of p-doped silicon, p-doped germanium, p-doped silicon germanium compounds, p-doped silicon carbide, p-doped silicon oxycarbide compounds, p-doped gallium nitride compounds, and p-doped gallium aluminum nitride compounds.

[0046] Alternatively, the first and the second plates 712 and 714 include metal plates selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold. Alternatively still, the first and the second plates 712 and 714 include metallic nitride plates selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride.

[0047] Also, as described above, embodiments of the present invention include a gate 709 that includes a metal gate 709 selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold. Alternatively, the gate 709 includes a metallic nitride gate 709 selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride. Alternatively still, the gate 709 includes a p-type polycrystalline semiconductor gate selected from the group consisting of p-doped silicon, p-doped germanium, p-doped silicon germanium compounds, p-doped silicon carbide, p-doped silicon oxycarbide compounds, p-doped gallium nitride compounds, and p-doped gallium aluminum nitride compounds.

[0048] In one embodiment of FIG. 7, the n-type well 731 is tied to a positive voltage which is less than a power supply voltage. In an alternative embodiment of FIG. 7, the n-type well 731 is tied to a voltage which is equal to a power supply voltage. In still another embodiment of the present invention, the n-type well 731 is tied to a voltage which is greater than a power supply voltage.

[0049] Using an array plate voltage of Vcc/2 serves to reduce the electric field across the capacitor dielectric to reduce dielectric leakage currents, like tunneling and reduce the probability of dielectric breakdown. Here however if the plates are made of different materials the array plate might be tied to Vcc and the large work function of the other individual capacitor plate used to reduce the tunneling leakage currents since there would either be no electric field or voltage across the dielectric when a 1 was stored in the capacitor or only a negative potential of magnitude Vcc when a zero is stored in the capacitor. If only a negative potential difference is used then the large work function plate material will reduce the tunneling leakage current. If both the array plate and capacitor plate are made of the same large work function material then an array plate potential of Vcc/2 can be used since either plate will have a large work function and it will be difficult to cause electron tunneling from either. If the array plate is not of the same material and is not a high work function material then an intermediate value of array plate potential other than Vcc/2 might be an optimum choice. The disclosure is not so limited. For purposes of illustration we will assume the plates are of the same material and the array plate is at a potential of Vcc/2. By using capacitor plate materials with large work functions, as shown in FIGS. 6 and 7, the tunneling leakage currents of the storage capacitors can be eliminated.

[0050] The use of a PMOS transfer device with a P+ source/drain region with a large work function will result in minimal tunneling currents to the gate or eliminate tunneling leakage currents. According to the teachings of the present invention, the P+ source/drain region can be formed of any of the semiconductor materials described herein having a large work function.

[0051] Tunneling leakage from the gate can be avoided or eliminated by using gate materials with a large work function. These tunneling currents can also be reduced by biasing the n-well at a more negative potential or less than the power supply voltage Vdd; however, this can result in extra transistor subthreshold leakage since the source to n-well will be forward biased. Biasing the n-well to a potential less than Vdd will however result in less source/drain junction leakage when a zero is stored in the cell since the reverse bias between the source/drain and well will be smaller. Biasing the n-well more positive or above Vdd will result in less junction leakage tending to reduce the cell capacitor plate to voltages below Vdd when a one is stored on the capacitor plate. A variety of well potentials can thus be employed to meet different application requirements and the disclosure is not so limited by any particular n-well potential.

[0052] The use of large work function capacitor electrode plate materials, large work function gate materials, and large work function P+ source/drain regions have been described for the elimination of direct band to band tunneling leakage currents in DRAM memory cells.

[0053] Methods of the Invention

[0054] As will be understood by one of ordinary skill in the art upon reading and studying this disclosure the following methods are included as part of the scope of the present invention. These methods can be fully understood and practiced in reference to the Figures described in detail above. A first method includes a method of forming a memory cell. This method includes forming a PMOS transistor an n-type well. Forming the PMOS transistor includes forming a first and a second source/drain regions separated by a channel. Forming the first and the second source/drain regions includes forming source/drain regions having a large work function. The method further includes forming a gate opposing the channel. According to the teachings of the present invention, forming the gate includes forming a gate having a work function of greater than 4.1 eV. A gate insulator is formed separating the gate from the channel. In one embodiment, the gate insulator is formed to a thickness of less than 20 Angstroms. Finally, the method includes forming a storage device coupled to the second source/drain region. Forming the storage device includes forming a storage device having a first and a second storage node separated by a dielectric. According to the teachings of the present invention at least one of the first and the second storage nodes has a large work function. In one embodiment, the at least one storage node having a large work function includes a work function greater than 4.1 eV.

[0055] In one embodiment of the above method, forming the PMOS transistor in an n-type well includes coupling the n-type well to a positive voltage which is less than a power supply voltage. In another embodiment of the above method forming the PMOS transistor in an n-type well includes coupling the n-type well to a voltage which is equal to a power supply voltage. In yet another embodiment of the above method forming the PMOS transistor in an n-type well includes coupling the n-type well to a voltage which is greater than a power supply voltage.

[0056] Further, in one embodiment forming the first and the second storage nodes includes forming the first and the second storage nodes of the same material. In one embodiment, forming the first and the second source/drain regions having a large work function includes forming the first and the second source/drain regions with a work function greater than 4.1 eV.

[0057] In one embodiment, forming the first and the second storage nodes includes forming first and second storage nodes which include a p-type polysilicon polycrystalline semiconductor material selected from the group consisting of p-doped silicon, p-doped germanium, p-doped silicon germanium compounds, p-doped silicon carbide, p-doped silicon oxycarbide compounds, p-doped gallium nitride compounds, and p-doped gallium aluminum nitride compounds.

[0058] Alternatively, in one embodiment, forming the first and the second storage nodes includes forming the first and the second storage nodes of a metal selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold.

[0059] Alternatively still, in one embodiment, forming the first and the second storage nodes includes forming the first and the second storage nodes of a metallic nitride selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride.

[0060] In one embodiment, forming the gate includes forming a metal gate selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold. In another embodiment of the above method forming the gate includes forming a metallic nitride gate selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride. In another embodiment of the above method forming the gate includes forming a p-type polycrystalline semiconductor gate selected from the group consisting of p-doped silicon, p-doped germanium, p-doped silicon germanium compounds, p-doped silicon carbide, p-doped silicon oxycarbide compounds, p-doped gallium nitride compounds, and p-doped gallium aluminum nitride compounds.

[0061] Another method embodiment of the present invention includes a method for operating a memory cell. This method includes applying a negative voltage to a gate of a PMOS transistor formed in an n-type well. In this embodiment, the PMOS transistor includes a first source/drain region and a second source/drain region. The first and the second source/drain region include source/drain regions having a large work function. A channel is located between the first and the second source/drain regions. A gate opposes the channel. In one embodiment, the gate includes a gate having a large work function. A gate insulator separates the gate from the channel. In one embodiment, the gate insulator is less than 20 Angstroms thick. The method further includes coupling the n-type well to a positive voltage which is less than a power supply voltage. The method further includes reading a charge level of a storage device. The storage device includes a first and a second storage node. At least one of the first and the second storage nodes is formed of a material having a large work function.

[0062] According to the teachings of the present invention, coupling the n-type well to a positive voltage which is less than a power supply voltage achieves lower tunneling charge leakage from the gate.

[0063] Another method embodiment for the present invention includes a method for operating a memory cell. This method includes applying a negative voltage to a gate of a PMOS transistor formed in an n-type well. Again, the PMOS transistor includes a first source/drain region and a second source/drain region. The first and the second source/drain region include source/drain regions having a large work function. A channel located between the first and the second source/drain regions. A gate opposes the channel. In one embodiment, the gate includes a gate having a large work function. A gate insulator separates the gate from the channel. In one embodiment, the gate insulator is less than 20 Angstroms thick. The method further includes coupling the n-type well to a voltage which is equal to a power supply voltage. And, the method includes reading a charge level of a storage device. The storage device includes a first and a second storage node. In one embodiment, at least one of the first and the second storage nodes includes a storage node formed of a material having a large work function.

[0064] According to the teachings of the present invention, coupling the n-type well to a voltage which is equal to a power supply voltage achieves lower tunneling charge leakage from the gate and lower junction leakage from the second source/drain region and storage device when the storage device is not charged.

[0065] Another method embodiment of the present invention includes a method for operating a memory cell. This embodiment includes applying a negative voltage to a gate of a PMOS transistor formed in an n-type well. The PMOS transistor includes a first source/drain region and a second source/drain region. The first and the second source/drain region include source/drain regions formed of a material having a large work function. A channel is located between the first and the second source/drain regions and a gate opposes the channel. In one embodiment, the gate includes a gate having a large work function. A gate insulator separates the gate from the channel. In one embodiment, the gate insulator is less than 20 Angstroms thick. The method further includes coupling the n-type well to a voltage which is greater than a power supply voltage. The method further includes reading a charge level of a storage device. The storage device includes a first and a second storage node. In one embodiment, the first and the second storage nodes includes at least one storage node formed of a material having a large work function.

[0066] According to the teachings of the present invention, coupling the n-type well to a voltage which is greater than a power supply voltage will result in less junction leakage tending to reduce the cell capacitor plate to voltages below Vdd when a one is stored on the capacitor plate.

[0067] As such, one of ordinary skill in the art will understand upon reading this disclosure that a variety of well potentials can thus be employed to meet different application requirements and this disclosure in not so limited by any particular n-well 731 potential.

CONCLUSION

[0068] The above structures and fabrication methods have been described, by way of example and not by way of limitation, with respect to provide improved techniques for controlling tunneling currents in DRAM capacitors, cells and devices. Such improved techniques should take into power supply currents and power dissipation issues. 

What is claimed is:
 1. A PMOS transistor, comprising: a first source/drain region; a second source/drain region, wherein the first and the second source/drain region include source/drain regions having a large work function; a channel located between the first and the second source/drain regions; a gate opposing the channel, wherein the gate includes a p-type polycrystalline semiconductor gate having a large work function; and a gate insulator separating the gate from the channel.
 2. The PMOS transistor of claim 1, wherein the polycrystalline semiconductor gate includes p-doped silicon.
 3. The PMOS transistor of claim 1, wherein the polycrystalline semiconductor gate includes p-doped germanium.
 4. The PMOS transistor of claim 1, wherein the polycrystalline semiconductor gate includes p-doped silicon germanium compounds.
 5. The PMOS transistor of claim 1, wherein the polycrystalline semiconductor gate includes p-doped silicon carbide.
 6. The PMOS transistor of claim 1, wherein the polycrystalline semiconductor gate includes a semiconductor gate selected from the group consisting of p-doped gallium nitride and p-doped gallium aluminum nitride compounds.
 7. A PMOS transistor, comprising: first source/drain region; a second source/drain region, wherein the first and the second source/drain region include source/drain regions having a large work function; a channel located between the first and the second source/drain regions; a gate opposing the channel, wherein the gate includes a metal gate having a large work function; and a gate insulator separating the gate from the channel.
 8. The PMOS transistor of claim 7, wherein the metal gate includes a metal gate selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold.
 9. The PMOS transistor of claim 7, wherein the metal gate includes a metallic nitride gate selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride.
 10. The PMOS transistor of claim 7, wherein the transistor forms part of a memory cell.
 11. The PMOS transistor of claim 7, wherein the transistor forms part of a DRAM cell.
 12. The PMOS transistor of claim 7, wherein the gate insulator is less than 20 Angstroms thick.
 13. A memory cell, comprising: a PMOS transistor, wherein the PMOS transistor first source/drain region; a second source/drain region, wherein the first and the second source/drain region include source/drain regions; a channel located between the first and the second source/drain regions; a gate opposing the channel; and a gate insulator separating the gate from the channel; and a capacitor coupled to the second source/drain region wherein a first and a second plate of the capacitor include first and second plates having a large work function.
 14. The memory cell of claim 13, wherein the first and the second plates include p-type polysilicon polycrystalline semiconductor plates.
 15. The memory cell of claim 14, wherein the polycrystalline semiconductor plates are selected from the group consisting of p-doped silicon, p-doped germanium, p-doped silicon germanium compounds, p-doped silicon carbide, p-doped silicon oxycarbide compounds, p-doped gallium nitride compounds, and p-doped gallium aluminum nitride compounds.
 16. The memory cell of claim 13, wherein the first and the second plates include metal plates.
 17. The memory cell of claim 16, wherein the metal plates include metal plates selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold.
 18. The memory cell of claim 13, wherein the first and the second plates include metallic nitride plates.
 19. The memory cell of claim 18, wherein the metallic nitride plates include metallic nitride plates selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride.
 20. A memory cell, comprising: a PMOS transistor, wherein the PMOS transistor includes: first source/drain region; a second source/drain region, wherein the first and the second source/drain region include source/drain regions having a large work function; a channel located between the first and the second source/drain regions; a gate opposing the channel, wherein the gate includes a gate having a large work function; and a gate insulator separating the gate from the channel, wherein the gate insulator is less than 20 Angstroms thick; and a capacitor coupled to the second source/drain region wherein a first and a second plate of the capacitor include first and second plates having a large work function.
 21. The memory cell of claim 20, wherein the first and the second plates include p-type polysilicon polycrystalline semiconductor plates selected from the group consisting of p-doped silicon, p-doped germanium, p-doped silicon germanium compounds, p-doped silicon carbide, p-doped silicon oxycarbide compounds, p-doped gallium nitride compounds, and p-doped gallium aluminum nitride compounds.
 22. The memory cell of claim 20, wherein the first and the second plates include metal plates selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold.
 23. The memory cell of claim 20, wherein the first and the second plates include metallic nitride plates selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride.
 24. The memory cell of claim 20, wherein the gate includes a metal gate selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold.
 25. The memory cell of claim 20, wherein the gate includes a metallic nitride gate selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride.
 26. The memory cell of claim 20, wherein the gate includes a p-type polycrystalline semiconductor gate selected from the group consisting of p-doped silicon, p-doped germanium, p-doped silicon germanium compounds, p-doped silicon carbide, p-doped silicon oxycarbide compounds, p-doped gallium nitride compounds, and p-doped gallium aluminum nitride compounds.
 27. A memory cell, comprising: a PMOS transistor formed in an n-type well, wherein the n-type well is tied to a positive voltage which is less than a power supply voltage, wherein the PMOS transistor includes: first source/drain region; a second source/drain region, wherein the first and the second source/drain region include source/drain regions having a large work function; a channel located between the first and the second source/drain regions; a gate opposing the channel, wherein the gate includes a p-type polycrystalline semiconductor gate having a large work function; and a gate insulator separating the gate from the channel, wherein the gate insulator is less than 20 Angstroms thick; and a capacitor coupled to the second source/drain region wherein a first and a second plate of the capacitor include first and second plates having a large work function.
 28. The memory cell of claim 27, wherein the first and the second plates include p-type polysilicon polycrystalline semiconductor plates selected from the group consisting of p-doped silicon, p-doped germanium, p-doped silicon germanium compounds, p-doped silicon carbide, p-doped silicon oxycarbide compounds, p-doped gallium nitride compounds, and p-doped gallium aluminum nitride compounds.
 29. The memory cell of claim 27, wherein the first and the second plates include metal plates selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold.
 30. The memory cell of claim 27, wherein the first and the second plates include metallic nitride plates selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride.
 31. The memory cell of claim 27, wherein the gate includes a metal gate selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold.
 32. The memory cell of claim 27, wherein the gate includes a metallic nitride gate selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride.
 33. The memory cell of claim 27, wherein the gate includes a p-type polycrystalline semiconductor gate selected from the group consisting of p-doped silicon, p-doped germanium, p-doped silicon germanium compounds, p-doped silicon carbide, p-doped silicon oxycarbide compounds, p-doped gallium nitride compounds, and p-doped gallium aluminum nitride compounds.
 34. A memory cell, comprising: a PMOS transistor formed in an n-type well, wherein the n-type well is tied to a voltage which is equal to a power supply voltage, wherein the PMOS transistor includes: first source/drain region; a second source/drain region, wherein the first and the second source/drain region include source/drain regions having a large work function; a channel located between the first and the second source/drain regions; a gate opposing the channel, wherein the gate includes a p-type polycrystalline semiconductor gate having a large work function; and a gate insulator separating the gate from the channel, wherein the gate insulator is less than 20 Angstroms thick; and a capacitor coupled to the second source/drain region wherein a first and a second plate of the capacitor include first and second plates having a large work function.
 35. A memory cell, comprising: a PMOS transistor formed in an n-type well, wherein the n-type well is tied to a voltage which is greater than a power supply voltage, wherein the PMOS transistor includes: first source/drain region; a second source/drain region, wherein the first and the second source/drain region include source/drain regions having a large work function; a channel located between the first and the second source/drain regions; a gate opposing the channel, wherein the gate includes a p-type polycrystalline semiconductor gate having a large work function; and a gate insulator separating the gate from the channel, wherein the gate insulator is less than 20 Angstroms thick; and a capacitor coupled to the second source/drain region wherein a first and a second plate of the capacitor include first and second plates having a large work function.
 36. A method of forming a PMOS transistor, comprising: forming a first source/drain region; forming a second source/drain region, wherein forming the first and the second source/drain region includes forming source/drain regions having a large work function; forming a channel located between the first and the second source/drain regions; forming a gate opposing the channel, wherein forming the gate includes a forming a p-type polycrystalline semiconductor gate having a large work function; and forming a gate insulator separating the gate from the channel.
 37. The method of claim 36, wherein forming the polycrystalline semiconductor gate includes forming the polycrystalline gate from a material selected from the group consisting of p-doped silicon, p-doped germanium; p-doped silicon germanium compounds; p-doped silicon carbide; p-doped gallium nitride, and p-doped gallium aluminum nitride compounds.
 38. A method of forming a PMOS transistor, comprising: forming a first source/drain region; forming a second source/drain region, wherein forming the first and the second source/drain regions includes forming source/drain regions having a large work function; forming a channel located between the first and the second source/drain regions; forming a gate opposing the channel, wherein forming the gate includes forming a gate having a large work function; and forming a gate insulator separating the gate from the channel.
 39. The method of claim 38, wherein forming the gate includes a forming metal gate selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold.
 40. The method of claim 38, wherein forming the gate includes forming a metallic nitride gate selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride.
 41. The method of claim 38, wherein forming the gate insulator includes forming the gate insulator to have a thickness of less than 20 Angstroms.
 42. A method of forming a memory cell, comprising: forming a PMOS transistor, wherein forming the PMOS transistor includes; forming a first source/drain region; forming a second source/drain region, wherein forming the first and the second source/drain regions includes forming source/drain regions having a large work function; forming a channel located between the first and the second source/drain regions; forming a gate opposing the channel, wherein forming the gate includes forming a gate having a work function greater than 4.1 eV; and forming a gate insulator separating the gate from the channel; and forming a capacitor coupled to the second source/drain region wherein forming the capacitor includes forming a first and a second storage node, and wherein at least one of the first and second storage nodes is formed having a large work function.
 43. The method of claim 42, wherein the at least one storage node having a large work function includes a work function greater than 4.1 eV.
 44. The method of claim 42, wherein forming the first and the second storage nodes includes forming the first and the second storage nodes of the same material.
 45. The method of claim 42, wherein forming the first and the second source/drain regions having a large work function includes forming the first and the second source/drain regions with a work function greater than 4.1 eV.
 46. The method of claim 42, wherein forming the first and the second storage nodes includes forming first and second storage nodes which include a p-type polysilicon polycrystalline semiconductor material selected from the group consisting of p-doped silicon, p-doped germanium, p-doped silicon germanium compounds, p-doped silicon carbide, p-doped silicon oxycarbide compounds, p-doped gallium nitride compounds, and p-doped gallium aluminum nitride compounds.
 47. The method of claim 42, wherein forming the first and the second storage nodes includes forming the first and the second storage nodes of a metal selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold.
 48. The method of claim 42, wherein forming the first and the second storage nodes includes forming the first and the second storage nodes of a metallic nitride selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride.
 49. A method of forming a memory cell, comprising: forming a PMOS transistor, wherein forming the PMOS transistor includes: forming a first and a second source/drain regions separated by a channel, wherein forming the first and the second source/drain regions includes forming source/drain regions having a large work function; forming a gate opposing the channel, wherein forming the gate includes forming a gate having a work function of greater than 4.1 eV; and forming a gate insulator separating the gate from the channel, wherein the gate insulator is less than 20 Angstroms thick; and forming a storage device coupled to the second source/drain region, wherein forming the storage device includes forming a storage device having a first and a second storage node separated by a dielectric, and wherein at least one of the first and the second storage nodes has a large work function.
 50. The method of claim 49, wherein the at least one storage node having a large work function includes a work function greater than 4.1 eV.
 51. The method of claim 49, wherein forming the first and the second storage nodes includes forming the first and the second storage nodes of the same material.
 52. The method of claim 49, wherein forming the first and the second source/drain regions having a large work function includes forming the first and the second source/drain regions with a work function greater than 4.1 eV.
 53. The method of claim 42, wherein forming the first and the second storage nodes includes forming first and second storage nodes which include a p-type polysilicon polycrystalline semiconductor material selected from the group consisting of p-doped silicon, p-doped germanium, p-doped silicon germanium compounds, p-doped silicon carbide, p-doped silicon oxycarbide compounds, p-doped gallium nitride compounds, and p-doped gallium aluminum nitride compounds.
 54. The method of claim 42, wherein forming the first and the second storage nodes includes forming the first and the second storage nodes of a metal selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold.
 55. The method of claim 42, wherein forming the first and the second storage nodes includes forming the first and the second storage nodes of a metallic nitride selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride.
 56. The method of claim 49, wherein forming the gate includes forming a metal gate selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold.
 57. The method of claim 49, wherein forming the gate includes forming a metallic nitride gate selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride.
 58. The method of claim 49, wherein forming the gate includes forming a p-type polycrystalline semiconductor gate selected from the group consisting of p-doped silicon, p-doped germanium, p-doped silicon germanium compounds, p-doped silicon carbide, p-doped silicon oxycarbide compounds, p-doped gallium nitride compounds, and p-doped gallium aluminum nitride compounds.
 59. A method of forming a memory cell, comprising: forming a PMOS transistor an n-type well, wherein forming the PMOS transistor includes: forming a first and a second source/drain regions separated by a channel, wherein forming the first and the second source/drain regions includes forming source/drain regions having a large work function; forming a gate opposing the channel, wherein forming the gate includes forming a gate having a work function of greater than 4.1 eV; and forming a gate insulator separating the gate from the channel, wherein the gate insulator is less than 20 Angstroms thick; and forming a storage device coupled to the second source/drain region, wherein forming the storage device includes forming a storage device having a first and a second storage node separated by a dielectric, and wherein at least one of the first and the second storage nodes has a large work function.
 60. The method of claim 59, wherein forming the PMOS transistor in an n-type well includes coupling the n-type well to a positive voltage which is less than a power supply voltage.
 61. The method of claim 59, wherein forming the PMOS transistor in an n-type well includes coupling the n-type well to a voltage which is equal to a power supply voltage.
 62. The method of claim 59, wherein forming the PMOS transistor in an n-type well includes coupling the n-type well to a voltage which is greater than a power supply voltage.
 63. The method of claim 59, wherein the at least one storage node having a large work function includes a work function greater than 4.1 eV.
 64. The method of claim 59, wherein forming the first and the second storage nodes includes forming the first and the second storage nodes of the same material.
 65. The method of claim 59, wherein forming the first and the second source/drain regions having a large work function includes forming the first and the second source/drain regions with a work function greater than 4.1 eV.
 66. The method of claim 59, wherein forming the first and the second storage nodes includes forming first and second storage nodes which include a p-type polysilicon polycrystalline semiconductor material selected from the group consisting of p-doped silicon, p-doped germanium, p-doped silicon germanium compounds, p-doped silicon carbide, p-doped silicon oxycarbide compounds, p-doped gallium nitride compounds, and p-doped gallium aluminum nitride compounds.
 67. The method of claim 59, wherein forming the first and the second storage nodes includes forming the first and the second storage nodes of a metal selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold.
 68. The method of claim 59, wherein forming the first and the second storage nodes includes forming the first and the second storage nodes of a metallic nitride selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride.
 69. The method of claim 59, wherein forming the gate includes forming a metal gate selected from the group consisting of cobalt, nickel, rubinium, rhodium, palladium, iridium, platinum and gold.
 70. The method of claim 59, wherein forming the gate includes forming a metallic nitride gate selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and molybdenum nitride.
 71. The method of claim 59, wherein forming the gate includes forming a p-type polycrystalline semiconductor gate selected from the group consisting of p-doped silicon, p-doped germanium, p-doped silicon germanium compounds, p-doped silicon carbide, p-doped silicon oxycarbide compounds, p-doped gallium nitride compounds, and p-doped gallium aluminum nitride compounds.
 72. A method for operating a memory cell, comprising: applying a negative voltage to a gate of a PMOS transistor formed in an n-type well, wherein the PMOS transistor includes: first source/drain region; a second source/drain region, wherein the first and the second source/drain region include source/drain regions having a large work function; a channel located between the first and the second source/drain regions; a gate opposing the channel, wherein the gate includes a gate having a large work function; and a gate insulator separating the gate from the channel, wherein the gate insulator is less than 20 Angstroms thick; and; coupling the n-type well to a positive voltage which is less than a power supply voltage; and reading a charge level of a storage device, wherein the storage device includes a first and a second storage node, the first and the second storage nodes having a large work function.
 73. The method of claim 36, wherein coupling the n-type well to a positive voltage which is less than a power supply voltage achieves lower tunneling charge leakage from the gate.
 74. A method for operating a memory cell, comprising: applying a negative voltage to a gate of a PMOS transistor formed in an n-type well, wherein the PMOS transistor includes: first source/drain region; a second source/drain region, wherein the first and the second source/drain region include source/drain regions having a large work function; a channel located between the first and the second source/drain regions; a gate opposing the channel, wherein the gate includes a gate having a large work function; and a gate insulator separating the gate from the channel, wherein the gate insulator is less than 20 Angstroms thick; and; coupling the n-type well to a voltage which is equal to a power supply voltage; and reading a charge level of a storage device, wherein the storage device includes a first and a second storage node, the first and the second storage nodes having a large work function.
 75. The method of claim 36, wherein coupling the n-type well to a voltage which is equal to a power supply voltage achieves lower tunneling charge leakage from the gate and lower junction leakage from the second source/drain region and storage device when the storage device is not charged.
 76. A method for operating a memory cell, comprising: applying a negative voltage to a gate of a PMOS transistor formed in an n-type well, wherein the PMOS transistor includes: first source/drain region; a second source/drain region, wherein the first and the second source/drain region include source/drain regions having a large work function; a channel located between the first and the second source/drain regions; a gate opposing the channel, wherein the gate includes a gate having a large work function; and a gate insulator separating the gate from the channel, wherein the gate insulator is less than 20 Angstroms thick; and; coupling the n-type well to a voltage which is greater than a power supply voltage; and reading a charge level of a storage device, wherein the storage device includes a first and a second storage node, the first and the second storage nodes having a large work function.
 77. The method of claim 36, wherein coupling the n-type well to a positive voltage which is greater than a power supply voltage results in less junction leakage the first and second source/drain regions. 